Modern computer architectures share physical resources between different programs in order to increase area-, energy-, and cost- efficiency. Unfortunately, sharing often gives rise to side channels that can be exploited for extracting or transmitting sensitive information. We currently lack techniques for systematic reasoning about this interplay between security and efficiency. In particular, there is no established way for quantifying security properties of shared caches. In this paper, we propose a novel model that enables us to characterize important security properties of caches. Our model encompasses two aspects: (1) The amount of information that can be absorbed by a cache, and (2) the amount of information that can effectively be ex...
We expand on the idea, proposed by Kelsey et al. [14], of cache memory being used as a side-channel ...
Software cache-based side channel attacks are a serious new class of threats for computers. Unlike p...
The sensitivity of a cache replacement policy expresses to what extent the execution history may inf...
Modern computer architectures share physical resources between different programs in order to increa...
We present CacheAudit, a versatile framework for the automatic, static analysis of cache side channe...
Abstract—This paper proposes an efficient cache line management algorithm for a security-aware cache...
Cache attacks exploit the hardware vulnerabilities inherent to modern processors and pose a new thre...
We present CacheAudit, a versatile framework for the automatic, static analysis of cache side channe...
International audienceModern processors use cache memory: a memory access that “hits” the cache retu...
In this paper, we propose a cache architecture, called SCache, to detect buffer-overflow attacks at ...
Security and trustworthiness are key considerations in designing modern processor hardware. It has b...
© 2020 Copyright held by the owner/author(s). Publication rights licensed to ACM. The hardware secur...
© 2020 IEEE. It is well known that there are micro-architectural vulnerabilities that enable an atta...
International audienceThe static analysis of cache accesses consists in correctly predicting which a...
Over the last decades the digitalization has become an integral part of daily life. Computer systems...
We expand on the idea, proposed by Kelsey et al. [14], of cache memory being used as a side-channel ...
Software cache-based side channel attacks are a serious new class of threats for computers. Unlike p...
The sensitivity of a cache replacement policy expresses to what extent the execution history may inf...
Modern computer architectures share physical resources between different programs in order to increa...
We present CacheAudit, a versatile framework for the automatic, static analysis of cache side channe...
Abstract—This paper proposes an efficient cache line management algorithm for a security-aware cache...
Cache attacks exploit the hardware vulnerabilities inherent to modern processors and pose a new thre...
We present CacheAudit, a versatile framework for the automatic, static analysis of cache side channe...
International audienceModern processors use cache memory: a memory access that “hits” the cache retu...
In this paper, we propose a cache architecture, called SCache, to detect buffer-overflow attacks at ...
Security and trustworthiness are key considerations in designing modern processor hardware. It has b...
© 2020 Copyright held by the owner/author(s). Publication rights licensed to ACM. The hardware secur...
© 2020 IEEE. It is well known that there are micro-architectural vulnerabilities that enable an atta...
International audienceThe static analysis of cache accesses consists in correctly predicting which a...
Over the last decades the digitalization has become an integral part of daily life. Computer systems...
We expand on the idea, proposed by Kelsey et al. [14], of cache memory being used as a side-channel ...
Software cache-based side channel attacks are a serious new class of threats for computers. Unlike p...
The sensitivity of a cache replacement policy expresses to what extent the execution history may inf...