On the variable step size gear integration method: Sudden time step variations induce inaccuracy

We deal with the well known and largely adopted Gear integration method that belongs to the class of linear multi-step integration algorithms. We consider its application in circuit simulations and highlight a drawback: The computation of its coefficients, even when the order 2 is selected, is affected by round-off errors in case that current integration time step is largely increased or decreased with respect to the previously used ones. As a consequence, inaccuracy is introduced in the solution that in turn may cause the rejection of the solution itself. If the time step had been decreased too rapidly, failure in the computation of the solution leads to further shortening of the time step and this can trigger an avalanche mechanism that can lead the simulation to fail or, in the best case, to a drop of simulation efficiency. On the contrary, if the time step had increased too rapidly, once more the computation of the solution may fail leading to shortening of the time step; this case is less problematic than the former but still reduces simulation efficiency