Schematization of CUDA architecture.

<p>Schematic representation of CUDA threads and memory hierarchy. <i>Left side</i>. Thread organization: a single kernel is launched from the host (the CPU) and is executed in multiple threads on the device (the GPU); threads can be organized in three-dimensional structures named blocks which can be, in turn, organized in three-dimensional grids. The dimensions of blocks and grids are explicitly defined by the programmer. <i>Right side</i>. Memory hierarchy: threads can access data from many different memories with different scopes; registers and local memories are private for each thread. Shared memory let threads belonging to the same block communicate, and has low access latency. All threads can access the global memory, which suffers of high latencies but is cached since the introduction of Fermi architecture. Texture and constant memories can be read from any thread and feature a cache as well. Figures are taken from the Nvidia's CUDA programming guide <a href="http://www.plosone.org/article/info:doi/10.1371/journal.pone.0091963#pone.0091963-NVIDIA2" target="_blank">[58]</a>.