Wafer-level packaging technology for RF applications based on a rigid low-loss spacer substrate

As mobile portable devices such as cellular system/phones, smart handheld devices and laptop computers acquire wireless connectivity there is a growing demand for greater levels of RF integration. The holy grail of integration is to have a whole set of different components integrated into one chip. However, for RF front-end the problem is the passive device integration. Moreover, protection of noise-sensitive analog circuits from "noisy" digital circuits becomes increasingly difficult for highly integrated components. To meet these challenges new enabling packaging technologies may be considered. The cost of wireless communications systems is often quoted as a most important driver. Thus, wafer-level packaging (WLP) may be considered as a promising solution to cost-effective RF system manufacturing, due to substantial cost savings with WLP's massively parallel processing and testing potential. In this thesis a wafer-level packaging concept based on a rigid spacer technology is proposed, that addresses both the issue of high-Q passive device integration and of on-chip isolation.Electrical Engineering, Mathematics and Computer Scienc