FPGA Realization of Low Register Systolic Multipliers over GF(2^m)

Finite field multiplication over GF(2^m) is a critical component for elliptic curve cryptography (ECC). National Institute of Standards and Technology (NIST) has recommended five polynomials (two trinomials and three pentanomials) for ECC implementation. Although there are a lot reports available on polynomial basis multipliers, efficient implementation of a design with flexible field-size is quite rare. There is another basis to represent the field called normal basis. Normal basis multiplication over GF(2^m) is widely used in various applications such as elliptic curve cryptography (ECC). As a special class of normal basis with low complexity, Gaussian normal basis (GNB) has received considerable attention recently. In this paper, we first propose a novel low-complexity hybrid-size systolic polynomial basis multiplier based on a proposed novel hybrid-size (for both pentanomial and trinomial) algorithm for efficient systolization of finite field multiplications. Next, we propose a novel decomposition algorithm to develop a digit-level (DL) low critical-path delay and low register-complexity systolic structure for GNB multiplication over GF(2^m). For the hybrid-size systolic polynomial multipliers, both the theoretical and field-programmable gate array (FPGA) implementation show that, our proposed architectures have lower register-complexity than the existing ones. The proposed hybrid-size multiplier can also be extended to other field-size and can be used as a third-party intellectual property (IP) core for various cryptosystems. At the same time, the proposed systolic Gaussian normal basis multipliers can achieve both low critical-path and low register-complexity through the theoretical and application-specific integrated circuit (ASIC) comparisons with the existing GNB multipliers