Large Scale Fabrication of Field-Effect Devices based on In Situ Grown Carbon Nanotubes

Since the first integrated circuits in the late 1960’s, a constant improvement of their performances could be reached by scaling down the metal oxide semiconductor field-effect transistors (MOSFETs). However, downscaling of MOS transistors has reached its physical limits: the gate oxide is only composed of a few atomic layers, leakage currents are increasing and the short channel effects degrade device properties. These are the reasons why new integration concepts need to be developed to replace silicon based Nanoelectronics. One of these concepts involves carbon nanotube field-effect transistors (CNTFETs). The active part of CNTFETs, i.e., the channel, is formed by a semiconducting single-walled carbon nanotube (SWNT), the growth of which represents one of the great challenges of CNT technology. Most publications on this topic report on a separate growth of nanotubes, either by arc discharge or laser ablation. These methods are not suitable for the fabrication of a large number of devices because they often require complicated manipulation and assembly after growth. Due to the improper growth method, state-of-the-art CNTFETs are mostly only single prototypes. Data on fabrication process suitability (e.g. time, costs), device reproducibility and reliability or yield are not available. However, a candidate for replacing MOSFET should not only have better performances but it should also be possible to produce it in large quantities to allow integration on a very large scale, i.e., billions of transistors on one wafer. Improving the knowledge of the scientific community on the feasibility of large scale fabrication of carbon nanotube devices constitutes the major motivation of this PhD work. The primary aim of this PhD work is the development of a CMOS compatible fabrication process for CNTFETs which allows large scale production of good quality devices within a reasonable time. For this, an in situ growth method for SWNTs has been developed, based on the catalytic chemical vapor deposition (CCVD) of carbon from methane. In situ means that the SWNTs directly grow in their final position on the wafer. The controlled growth of 1 nm diameter SWNTs by CCVD on oxidized silicon substrates covered by a catalytic layer composed of nickel on aluminum has been demonstrated. All SWNT diameter and density measurements have been performed by AFM, which has been found to be a very useful method for non-destructive geometrical and structural characterizations of SWNTs at the nanometer scale. To the best of our knowledge, successful conductive-AFM (C-AFM) measurements have been performed on in situ connected SWNTs for the first time worldwide. This allows clear overviews of SWNTs and structures also on rough underlayers, which are impossible with the traditional AFM due to the nanometer size of the SWNTs. The in situ growth of SWNTs has been integrated into a novel fabrication process for palladiumcontacted and PMMA (polymethyl methacrylate) passivated CNTFETs, which only requires one lithography step, avoiding any misalignment problems. The major novelty of the process consists in the introduction of a sacrificial catalyst, which is evaporated on the whole wafer surface. This catalyst is composed of a well-optimized Ni/Al bilayer, which catalyzes the growth of 1 nm diameter SWNTs and simultaneously transforms itself into an insulator (aluminum oxide covered with nickel nanoclusters) during the high temperature growth process, so that there is no need to structure the catalyst after deposition. The definition of the Pd source and drain regions as well as the passivation of the channel region occur simultaneously after the SWNT growth step by means of a single optical lithography step. The novel self-aligned fabrication process developed in this PhD thesis allows the simultaneous fabrication of approximately 1,000 transistors on one wafer (2''). Further optimization of the lithography layout could easily multiply this number. When comparing to the often practiced production of CNTFETs with external growth of SWNTs and subsequent coating or placement, this process based on the in situ growth method is more reliable and time-saving. It also reduces the risk of contamination of SWNTs, which leads to better device performance. The suitability for mass fabrication of this process has been verified on more than 15,000 devices. Extended yield statistics on 700 devices have been performed, leading to the result of 41% of fully functional high on/off ratio devices within all measured devices. Optimization of the device geometry, e.g. reduction of the effective channel length, should further improve the yield drastically. Approximately 100 devices have been completely evaluated, i.e., complete sets of electrical device characteristics have been recorded and analysed to perform statistics on device performance and reliability. The devices exhibit promising electrical parameters, e.g. on-currents up to 6 mA/µm and on/off ratios up to 2.6e7, already at a very low drain source bias of -400 mV. Such a low-voltage low-power technology is compatible with mobile applications. Moreover, the PMMA passivation increases the life time from some weeks to several years. The well-known hysteresis-effect in CNTFET electrical characteristics has been found to be a stable and reproducible phenomenon. It most likely originates from electron trapping and detrapping in the underlaying sacrificial oxide, i.e., the aluminum oxide. Due to their charge storing properties, CNTFETs are very suitable candidates to be used in memory applications. The operation as memory cells of the CNTFETs fabricated within this work has been tested extensively. As a result, the current ratio at the reading voltage between the logical "1" level (high current) and the logical "0" (low current) is up to 1e6 which is, to the best of our knowledge, the highest current ratio of logical levels ever published for CNT memory cells. The "0" and "1" current levels are temporally stable indicating the possibility for non-volatile memory usage. This PhD work clearly attests to the potential for large scale manufacturing of good quality CNTFETs for future industrial applications. Moreover, the process is also a remarkable technology platform for research on CNT electronics because a large number of devices can be realized easily and in a short time. This opens the possibility to investigate the influence of numerous fabrication parameters or environmental impacts on CNTFET electrical characteristics and reliability. Lastly, the suitability of CNTFETs used as sensors, e.g. infrared-sensors, gas-sensor or bio-sensors, could be easily investigated in the future using the CNTFET fabrication process developed within this work