High-Throughput Contention-Free Concurrent Interleaver Architecture for Multi-Standard Turbo Decoder

Abstract—To meet the higher data rate requirement of emerging wireless communication technology, numerous paral-lel turbo decoder architectures have been developed. However, the interleaver has become a major bottleneck that limits the achievable throughput in the parallel decoders due to the massive memory conflicts. In this paper, we propose a flexible Double-Buffer based Contention-Free (DBCF) inter-leaver architecture that can efficiently solve the memory conflict problem for parallel turbo decoders with very high parallelism. The proposed DBCF architecture enables high throughput concurrent interleaving for multi-standard turbo decoders that support UMTS/HSPA+, LTE and WiMAX, with small data-path delays and low hardware cost. We implemented the DBCF interleaver with a 65nm CMOS technology. The implementa-tion of this highly efficient DBCF interleaver architecture shows significant improvement in terms of the maximum throughput and occupied chip area compared to the previous work. Keywords-Parallel turbo decoder, interleaver, contention-free, UMTS, HSPA+, LTE, WiMAX, multi-standard I