Intra-Task Dynamic Cache Reconfiguration

Optimization techniques are widely used in embedded systems design to improve overall area, performance and energy requirements. Dy-namic cache reconfiguration (DCR) is very effective to reduce energy consumption of cache subsystems. Finding the right reconfiguration points in a task and selecting appropriate cache configurations for each phase are the primary challenges in phase-based DCR. In this paper, we present a novel intra-task dynamic cache reconfiguration technique using a detailed cache model, and tune a highly-configurable cache on a per-phase basis compared to tuning once per application. Experi-mental results demonstrate that our intra-task DCR can achieve up to 27 % (12 % on average) and 19 % (7 % on average) energy savings for instruction and data caches, respectively, without introducing any performance penalty.1 1