Implementations of Reconfigurable Logic Arrays on FPGAs

This paper presents a method to implement a reconfig-urable logic array on an FPGA. To design circuits with 2-valued k-input LUTs, 2k-valued logic is introduced. Stan-dard benchmark functions as well as symmetric functions are efficiently implemented by a logic array with 2k-valued variables. Number of products and number of bits to rep-resent functions by the expressions with 2k-valued vari-ables for k = 1, 2, 3, 4, and 5 are compared. Both sum-of-products expressions and EXOR sum-of-products expres-sions of 2k-valued logic significantly reduces needed FPGA resources, when 2 ≤ k ≤ 5. Experimental results for benchmark functions and symmetric functions are shown. Implementations of arrays with 16-valued variables on Xil-inx and Altera FPGAs are also shown. 1