Data transformations enabling loop vectorization on multithreaded data parallel architectures

Loop vectorization, a key feature exploited to obtain high perfor-mance on Single Instruction Multiple Data (SIMD) vector architec-tures, is significantly hindered by irregular memory access patterns in the data stream. This paper describes data transformations that allow us to vectorize loops targeting massively multithreaded data parallel architectures. We present a mathematical model that cap-tures loop-based memory access patterns and computes the most appropriate data transformations in order to enable vectorization. Our experimental results show that the proposed data transforma-tions can significantly increase the number of loops that can be vec-torized and enhance the data-level parallelism of applications. Our results also show that the overhead associated with our data trans-formations can be easily amortized as the size of the input data set increases. For the set of high performance benchmark kernels stud