Simplified vector-thread architectures for flexible and efficient data-parallel accelerators

This thesis explores a new approach to building data-parallel accelerators that is based on simplify-ing the instruction set, microarchitecture, and programming methodology for a vector-thread archi-tecture. The thesis begins by categorizing regular and irregular data-level parallelism (DLP), before presenting several architectural design patterns for data-parallel accelerators including the multiple-instruction multiple-data (MIMD) pattern, the vector single-instruction multiple-data (vector-SIMD) pattern, the single-instruction multiple-thread (SIMT) pattern, and the vector-thread (VT) pattern. Our recently proposed VT pattern includes many control threads that each manage their own array of microthreads. The control thread uses vector memory instructions to efficiently move data an