A novel kind of chaos, digital chaos is proposed, and an extremely simple circuit to generate frequency controlled digital chaos using two XOR gates driven by three square signals with mismatched frequencies and duty cycles is designed and implemented in FPGA, with the basic principle that the XOR being a difference circuit, amplifies the mismatches, leading to chaos generation. The presence of chaos is ascertained using Lyapunov Exponent and the effect of driving signal frequency on the chaotic nature is studied. The generated chaotic bit sequence is then tested for randomness using standard tests from the NIST Test Suite. It is found that the generated digital chaotic bit sequence is indeed random, proving capability of the proposed circu...
In this work a new random number generator circuit using continuous-time chaos is described. The cir...
This brief proposes a novel architecture of the chaotic pseudo-random bit generators (PRBGs) based o...
In this work an original CMOS implementation of a discrete-time deterministic-chaos algorithm for ra...
22nd IEEE Signal Processing and Communications Applications Conference (SIU) -- APR 23-25, 2014 -- K...
International audienceAs any well-designed information security application uses a very large quanti...
Lots of researches indicate that the inefficient generation of random numbers is a significant bottl...
A remarkable correlation between chaotic systems and cryptography has been established with sensitiv...
Due to the character of the original source materials and the nature of batch digitization, quality ...
Recently, a new class of circuits named Digital Nonlinear Oscillators (DNOs) has been proposed for t...
This paper presents a novel, real time, high speed and robust chaos-based pseudo random number gener...
Chaotic systems and chaos-based applications have been commonly used in the fields of engineering re...
The generation of random numbers is required in several applications, including Monte Carlo simulati...
based on chaotic systems is developed in this paper. The main goal of this paper is to increase the ...
4noThis chapter discusses the problem of "chaos generation", namely efficient techniques for the des...
We present the design and the validation by means of suitably improved randomness tests of two diffe...
In this work a new random number generator circuit using continuous-time chaos is described. The cir...
This brief proposes a novel architecture of the chaotic pseudo-random bit generators (PRBGs) based o...
In this work an original CMOS implementation of a discrete-time deterministic-chaos algorithm for ra...
22nd IEEE Signal Processing and Communications Applications Conference (SIU) -- APR 23-25, 2014 -- K...
International audienceAs any well-designed information security application uses a very large quanti...
Lots of researches indicate that the inefficient generation of random numbers is a significant bottl...
A remarkable correlation between chaotic systems and cryptography has been established with sensitiv...
Due to the character of the original source materials and the nature of batch digitization, quality ...
Recently, a new class of circuits named Digital Nonlinear Oscillators (DNOs) has been proposed for t...
This paper presents a novel, real time, high speed and robust chaos-based pseudo random number gener...
Chaotic systems and chaos-based applications have been commonly used in the fields of engineering re...
The generation of random numbers is required in several applications, including Monte Carlo simulati...
based on chaotic systems is developed in this paper. The main goal of this paper is to increase the ...
4noThis chapter discusses the problem of "chaos generation", namely efficient techniques for the des...
We present the design and the validation by means of suitably improved randomness tests of two diffe...
In this work a new random number generator circuit using continuous-time chaos is described. The cir...
This brief proposes a novel architecture of the chaotic pseudo-random bit generators (PRBGs) based o...
In this work an original CMOS implementation of a discrete-time deterministic-chaos algorithm for ra...