Transactional memory promises to make parallel programming easier than with fine-grained locking, while performing just as well. This performance claim is not always borne out because an applica-tion may violate a common-case assumption of the TM designer or because of external system effects. In order to help programmers assess the suitability of their code for transactional memory, this work introduces a formal model of transactional memory as well as a tool, called Syncchar. Syncchar can predict the speedup of a conversion from locks to transactions within 25 % for the STAMP benchmarks. Because getting good performance from transactions is more difficult than commonly appreciated, developers need tools to tune transactional performance. ...
This document is presented in fulfilment of the degree of \emph{Habilitation \`{a} Diriger des Reche...
Abstract — Programming to exploit the resources in a multicore system remains a major obstacle for b...
Software transactional memory (STM) is a promis-ing technique for controlling concurrency in mod-ern...
Exploiting thread-level parallelism has become a part of mainstream programming in recent years. Man...
The advent of multicore processors has put the performance of traditional parallel programming techn...
Writing applications that benefit from the massive computational power of future multicore chip mult...
Transactional memory is a promising technique for multithreaded synchronization and con-currency whi...
Transactional Memory (TM) is a new programming paradigm that offers an alternative to traditional lo...
Fundamental limits in integrated circuit technology are bringing about the acceptance that multi-cor...
Scaling processor performance with future technology nodes is essential to enable future application...
Transactional memory (TM), a new programming paradigm, is one of the latest approaches to write prog...
Transactional memory (TM) is a new optimistic synchronization technique which has the potential of m...
Programmers have traditionally used locks to synchronize concurrent access to shared data. Lock-base...
Chip Multithreading (CMT) processors promise to deliver higher performance by running more than one ...
Transactional memory is a promising technique for multithreaded synchronization and concurrency whic...
This document is presented in fulfilment of the degree of \emph{Habilitation \`{a} Diriger des Reche...
Abstract — Programming to exploit the resources in a multicore system remains a major obstacle for b...
Software transactional memory (STM) is a promis-ing technique for controlling concurrency in mod-ern...
Exploiting thread-level parallelism has become a part of mainstream programming in recent years. Man...
The advent of multicore processors has put the performance of traditional parallel programming techn...
Writing applications that benefit from the massive computational power of future multicore chip mult...
Transactional memory is a promising technique for multithreaded synchronization and con-currency whi...
Transactional Memory (TM) is a new programming paradigm that offers an alternative to traditional lo...
Fundamental limits in integrated circuit technology are bringing about the acceptance that multi-cor...
Scaling processor performance with future technology nodes is essential to enable future application...
Transactional memory (TM), a new programming paradigm, is one of the latest approaches to write prog...
Transactional memory (TM) is a new optimistic synchronization technique which has the potential of m...
Programmers have traditionally used locks to synchronize concurrent access to shared data. Lock-base...
Chip Multithreading (CMT) processors promise to deliver higher performance by running more than one ...
Transactional memory is a promising technique for multithreaded synchronization and concurrency whic...
This document is presented in fulfilment of the degree of \emph{Habilitation \`{a} Diriger des Reche...
Abstract — Programming to exploit the resources in a multicore system remains a major obstacle for b...
Software transactional memory (STM) is a promis-ing technique for controlling concurrency in mod-ern...