Stmbench7: a benchmark for software transactional memory

Software transactional memory (STM) is a promis-ing technique for controlling concurrency in mod-ern multi-processor architectures. STM aims to be more scalable than coarse-grained locking and easier to use than fine-grained locks. However, STM implementations have yet to demonstrate that their runtime overheads are acceptable. To date, empiric evaluations of these implementa-tions have suffered from the lack of realistic bench-marks. Measuring performance of an STM in an overly simplified setting can be at best uninforma-tive and at worst misleading as it may steer re-searchers to try to optimize irrelevant aspects of their implementations. This paper presents STMBench7: a benchmark for evaluating STM implementations. The under-lying data structure consists of a set of graphs and indexes intended to be suggestive of many com-plex applications, e.g., CAD/CAM. A collection of operations is supported to model a wide range of workloads and concurrency patterns. Companion locking strategies serve as a baseline for STM per-formance comparisons. STMBench7 strives for simplicity. Users may choose a workload, number of threads, bench-mark length, as well as the possibility of struc-ture modification and the nature of traversals of shared data structures. We illustrate the use of STMBench7 with an evaluation of a well-known software transactional memory implementation. ∗EPFL Technical Report LPD-REPORT-2006-xxx. A part of this work has been submitted for publication.