Abstract. We consider the problem of verifying deadlock freedom for symmet-ric cache coherence protocols. While there are multiple definitions of deadlock in the literature, we focus on a specific form of deadlock which is useful for the cache coherence protocol domain and consistent with the internal definition of deadlock in the Murphi model checker: we refer to this deadlock as a system-wide deadlock (s-deadlock). In s-deadlock, the entire system gets blocked and is unable to make any transition. Cache coherence protocols consist of N symmet-ric cache agents, where N is an unbounded parameter; thus the verification of s-deadlock freedom is naturally a parameterized verification problem. Parametrized verification techniques work by using ...
We introduce a number of techniques for establishing the deadlock freedom of concurrent systems. Our...
. We present two tests for analyzing deadlock for a class of communicating sequential processes. The...
Contains fulltext : 168686.pdf (publisher's version ) (Closed access
We consider the problem of verifying deadlock freedom for symmetric cache coherence protocols. While...
Cache coherency is one of the major issues in multicore systems. Formal methods, in particular model...
We propose a heuristic-based method for discovering inductive invariants in the parameterized verifi...
International audienceWe present a formal model built for verification of the hardware Tera-Scale AR...
AbstractIn recent years many techniques have been developed for automatically verifying concurrent s...
In this paper, we describe Teapot, a domain-specific language for writing cache coherence protocols....
The design of a cache-coherent distributed shared memory (CCDSM) system is complex and prone to erro...
Part 6: Session 5: Model CheckingInternational audienceWe present a sound but incomplete criterion f...
AbstractModel checking is a proven successful technology for verifying hardware. It works, however, ...
Abstract Performance modelling and verification are vital steps in the development cycle of any cach...
With the maturing of computer-aided verification technology, there is an emerging opportunity to dev...
Computers have brought us inestimable convenience in recent years. We have become dependent on them ...
We introduce a number of techniques for establishing the deadlock freedom of concurrent systems. Our...
. We present two tests for analyzing deadlock for a class of communicating sequential processes. The...
Contains fulltext : 168686.pdf (publisher's version ) (Closed access
We consider the problem of verifying deadlock freedom for symmetric cache coherence protocols. While...
Cache coherency is one of the major issues in multicore systems. Formal methods, in particular model...
We propose a heuristic-based method for discovering inductive invariants in the parameterized verifi...
International audienceWe present a formal model built for verification of the hardware Tera-Scale AR...
AbstractIn recent years many techniques have been developed for automatically verifying concurrent s...
In this paper, we describe Teapot, a domain-specific language for writing cache coherence protocols....
The design of a cache-coherent distributed shared memory (CCDSM) system is complex and prone to erro...
Part 6: Session 5: Model CheckingInternational audienceWe present a sound but incomplete criterion f...
AbstractModel checking is a proven successful technology for verifying hardware. It works, however, ...
Abstract Performance modelling and verification are vital steps in the development cycle of any cach...
With the maturing of computer-aided verification technology, there is an emerging opportunity to dev...
Computers have brought us inestimable convenience in recent years. We have become dependent on them ...
We introduce a number of techniques for establishing the deadlock freedom of concurrent systems. Our...
. We present two tests for analyzing deadlock for a class of communicating sequential processes. The...
Contains fulltext : 168686.pdf (publisher's version ) (Closed access