In this paper, we describe Teapot, a domain-specific language for writing cache coherence protocols. Cache coherence is of concern when parallel and distributed systems make local replicas of shared data to improve scalability and performance. In both distributed shared memory systems and distributed file systems, a coherence protocol maintains agreement among the replicated copies as the underlying data are modified by programs running on the system. Cache coherence protocols are notoriously difficult to implement, debug, and maintain. Moreover, protocols are not off-the-shelf, reusable components, because their details depend on the requirements of the system under consideration. The complexity of engineering coherence protocols can disco...
Thesis: S.M., Massachusetts Institute of Technology, Department of Electrical Engineering and Comput...
There are few published examples of the proof of correctness of a cache-coherence protocol expressed...
We propose a two-phase Imperative-Directive design methodology for designing cache coherence protoco...
In this paper, we describe Teapot, a domain-specific language for writing cache coherence protocols....
In this paper we describe our experience with Teapot [7], a domain-specific language for writing cac...
Recent shared-memory parallel computer systems offer the exciting possibility of customizing memory ...
. We address the problem of developing efficient cache coherence protocols implementing distributed ...
Cache coherence is one of the main challenges to tackle when designing a shared-memory multiprocesso...
Caches have the potential to provide multiprocessors with an automatic mechanism for reducing both n...
This thesis presents a new cache coherence protocol for shared bus multicache systems, and addresses...
We propose a twophase ImperativeDirective design methodology for designing cache coherence protocols...
[[abstract]]A cache coherence protocol for a multiprocessor system. Each processor in the system has...
Submitted to the University of London for the Degree of Doctor of Philosophy in Computer Scienc
Thesis (Ph. D.)--University of Washington, 1987Shared-memory multiprocessors offer increased computa...
Cache coherence protocols play an important role in the performance of distributed and centralized s...
Thesis: S.M., Massachusetts Institute of Technology, Department of Electrical Engineering and Comput...
There are few published examples of the proof of correctness of a cache-coherence protocol expressed...
We propose a two-phase Imperative-Directive design methodology for designing cache coherence protoco...
In this paper, we describe Teapot, a domain-specific language for writing cache coherence protocols....
In this paper we describe our experience with Teapot [7], a domain-specific language for writing cac...
Recent shared-memory parallel computer systems offer the exciting possibility of customizing memory ...
. We address the problem of developing efficient cache coherence protocols implementing distributed ...
Cache coherence is one of the main challenges to tackle when designing a shared-memory multiprocesso...
Caches have the potential to provide multiprocessors with an automatic mechanism for reducing both n...
This thesis presents a new cache coherence protocol for shared bus multicache systems, and addresses...
We propose a twophase ImperativeDirective design methodology for designing cache coherence protocols...
[[abstract]]A cache coherence protocol for a multiprocessor system. Each processor in the system has...
Submitted to the University of London for the Degree of Doctor of Philosophy in Computer Scienc
Thesis (Ph. D.)--University of Washington, 1987Shared-memory multiprocessors offer increased computa...
Cache coherence protocols play an important role in the performance of distributed and centralized s...
Thesis: S.M., Massachusetts Institute of Technology, Department of Electrical Engineering and Comput...
There are few published examples of the proof of correctness of a cache-coherence protocol expressed...
We propose a two-phase Imperative-Directive design methodology for designing cache coherence protoco...