PARTIAL SUMS GENERATION ARCHITECTURE FOR SUCCESSIVE CANCELLATION DECODING OF POLAR CODES

Polar codes are a new family of error correction codes for which efficient hardware architectures have to be defined for the encoder and the decoder. Polar codes are decoded using the successive cancellation decoding algorithm that includes partial sums computations. We take advantage of the recur-sive structure of polar codes to introduce an efficient partial sums computation unit that can also implements the encoder. The proposed architecture is synthesized for several code-lengths in 65nm ASIC technology. The area of the resulting design is reduced up to 26 % and the maximum working fre-quency is improved by 25%. Index Terms — FEC, polar codes, hardware architecture, successive cancellation decoding 1