Hardware architectures for successive cancellation decoding of polar codes

The recently-discovered polar codes are widely seen as a ma-jor breakthrough in coding theory. These codes achieve the capacity of many important channels under successive cancellation decoding. Motivated by the rapid progress in the theory of polar codes, we pro-pose a family of architectures for efficient hardware implementation of successive cancellation decoders. We show that such decoders can be implemented with O(n) processing elements and O(n) mem-ory elements, while providing constant throughput. We also pro-pose a technique for overlapping the decoding of several consecutive codewords, thereby achieving a significant speed-up factor. We fur-thermore show that successive cancellation decoding can be imple-mented in the logarithmic domain, thereby eliminating the multipli-cation and division operations and greatly reducing the complexity of each processing element. Index Terms — Polar codes, successive cancellation decoding, hardware implementation, VLSI. 1