Numerous approaches can be employed in exploiting computation power in processors such as superscalar, VLIW, SMT and multi-core on chip. In this paper, a UniCore VisoMT processor is proposed, which unifies VLIW and multithreading by providing an efficient control and data communication model, while offering explicit parallelisms for embedded applications. The architecture concurrently executes a main thread and several accelerative threads, coordinated by the main thread. A switch-based register-file is provided for fast data exchange between these accelerative threads. Moreover, a SMT helper function unit is employed for controlling and resource-sharing between accelerative threads, and an event-driven mechanism is introduced for synchroni...
Seventh International Symposium on High Performance Computer Architecture (HPCA-7), Work in Progress...
Multithreaded processors, having hardware support for the concurrent execution of fine-grained thre...
Multithreaded processors, having hardware support for the concurrent execution of fine-grained thre...
Several multithreading techniques have been proposed to reduce the resource underutilization in Very...
Several multithreading techniques have been proposed to reduce the resource underutilization in Very...
This paper analyzes the basic design issues of multithreaded processors and discusses how they may r...
This paper analyzes the basic design issues of multithreaded processors and discusses how they may r...
This paper analyzes the basic design issues of multithreaded processors and discusses how they may r...
Clustered VLIW embedded processors have become widespread due to benefits of simple hardware and low...
There are two fundamental problems to be solved in any scalable computer system: tolerate and hide l...
A simultaneous multithreading (SMT) processor can issue instructions from several threads every cycl...
This paper examines simultaneous multithreading, a technique per-mitting several independent threads...
Very Long Instruction Word (VLIW) processors are very popular in embedded and mobile computing domai...
This paper examines simultaneous multithreading, a technique per-mitting several independent threads...
This paper introduces the concept of a novel archi-tecture, SMTVLIW: Simultaneous Multithreading VLI...
Seventh International Symposium on High Performance Computer Architecture (HPCA-7), Work in Progress...
Multithreaded processors, having hardware support for the concurrent execution of fine-grained thre...
Multithreaded processors, having hardware support for the concurrent execution of fine-grained thre...
Several multithreading techniques have been proposed to reduce the resource underutilization in Very...
Several multithreading techniques have been proposed to reduce the resource underutilization in Very...
This paper analyzes the basic design issues of multithreaded processors and discusses how they may r...
This paper analyzes the basic design issues of multithreaded processors and discusses how they may r...
This paper analyzes the basic design issues of multithreaded processors and discusses how they may r...
Clustered VLIW embedded processors have become widespread due to benefits of simple hardware and low...
There are two fundamental problems to be solved in any scalable computer system: tolerate and hide l...
A simultaneous multithreading (SMT) processor can issue instructions from several threads every cycl...
This paper examines simultaneous multithreading, a technique per-mitting several independent threads...
Very Long Instruction Word (VLIW) processors are very popular in embedded and mobile computing domai...
This paper examines simultaneous multithreading, a technique per-mitting several independent threads...
This paper introduces the concept of a novel archi-tecture, SMTVLIW: Simultaneous Multithreading VLI...
Seventh International Symposium on High Performance Computer Architecture (HPCA-7), Work in Progress...
Multithreaded processors, having hardware support for the concurrent execution of fine-grained thre...
Multithreaded processors, having hardware support for the concurrent execution of fine-grained thre...