Abstract—We propose an architectural design methodology for designing formally verifiable cache coherence protocols, called Fractal Coherence. Properly designed to be fractal in behavior, the proposed family of cache coherence protocols can be formally verified correct for systems with an arbitrary number of cores, using existing, automated formal tools. We show, by designing and implementing a specific Fractal Coherence protocol, called TreeFractal, that Fractal Coherence protocols can attain comparable performance to traditional snooping and directory protocols
Cache coherence protocol scalability problem for parallel architecture is also a problem for on chip...
The notion of belief has been useful in reasoning about authentication protocols. In this paper, we ...
Parallel applications exhibit a wide variety of memory reference patterns. Designing a memory archit...
Abstract—We propose an architectural design methodology for designing formally verifiable cache cohe...
<p>The correctness of a cache coherence protocol is crucial to the system since a subtle bug in the ...
In this paper we describe our experience with Teapot [7], a domain-specific language for writing cac...
For power and performance reasons, multicores have become the dominant microprocessor architecture. ...
Cache coherence is one of the main challenges to tackle when designing a shared-memory multiprocesso...
Cache coherency is one of the major issues in multicore systems. Formal methods, in particular model...
In this paper, we describe Teapot, a domain-specific language for writing cache coherence protocols....
Caches have the potential to provide multiprocessors with an automatic mechanism for reducing both n...
This thesis presents a new cache coherence protocol for shared bus multicache systems, and addresses...
This invited paper argues that to facilitate formal verification, multiprocessor systems should (1) ...
Thesis (Ph. D.)--University of Rochester. Dept. of Computer Science, 2013.Chip multiprocessors conti...
We propose a twophase ImperativeDirective design methodology for designing cache coherence protocols...
Cache coherence protocol scalability problem for parallel architecture is also a problem for on chip...
The notion of belief has been useful in reasoning about authentication protocols. In this paper, we ...
Parallel applications exhibit a wide variety of memory reference patterns. Designing a memory archit...
Abstract—We propose an architectural design methodology for designing formally verifiable cache cohe...
<p>The correctness of a cache coherence protocol is crucial to the system since a subtle bug in the ...
In this paper we describe our experience with Teapot [7], a domain-specific language for writing cac...
For power and performance reasons, multicores have become the dominant microprocessor architecture. ...
Cache coherence is one of the main challenges to tackle when designing a shared-memory multiprocesso...
Cache coherency is one of the major issues in multicore systems. Formal methods, in particular model...
In this paper, we describe Teapot, a domain-specific language for writing cache coherence protocols....
Caches have the potential to provide multiprocessors with an automatic mechanism for reducing both n...
This thesis presents a new cache coherence protocol for shared bus multicache systems, and addresses...
This invited paper argues that to facilitate formal verification, multiprocessor systems should (1) ...
Thesis (Ph. D.)--University of Rochester. Dept. of Computer Science, 2013.Chip multiprocessors conti...
We propose a twophase ImperativeDirective design methodology for designing cache coherence protocols...
Cache coherence protocol scalability problem for parallel architecture is also a problem for on chip...
The notion of belief has been useful in reasoning about authentication protocols. In this paper, we ...
Parallel applications exhibit a wide variety of memory reference patterns. Designing a memory archit...