Hardware Transactional Memory for GPU Architectures

Graphics processor units (GPUs) are designed to efficiently exploit thread level parallelism (TLP), multiplexing execution of 1000s of concurrent threads on a relatively smaller set of single-instruction, multiple-thread (SIMT) cores to hide various long latency opera-tions. While threads within a CUDA block/OpenCL workgroup can communicate efficiently through an intra-core scratchpad memory, threads in different blocks can only communicate via global mem-ory accesses. Programmers wishing to exploit such communication have to consider data-races that may occur when multiple threads modify the same memory location. Recent GPUs provide a form of inter-block communication through atomic operations for sin-gle 32-bit/64-bit words. Although fine-grained locks can be con-structed from these atomic operations, synchronization using locks is prone to deadlock. In this paper, we propose to solve these prob-lems by extending GPUs to support transactional memory (TM). Major challenges include supporting 1000s of concurrent transac-tions and committing non-conflicting transactions in parallel. We propose KILO TM, a novel hardware TM design for GPUs that scales to 1000s of concurrent transactions. Without cache coherency hardware to depend on, it uses word-level, value-based conflict detection to avoid broadcast communication and reduce on-chip storage overhead. It employs speculative validation using a novel bloom filter organization to increase transaction commit parallelism. For a set of TM-enhanced GPU applications, KILO TM captures 59 % of the performance of fine-grained locking, and is on average 128 × faster than executing all transactions serially, for an estimated hardware area overhead of 0.5 % of a commercial GPU