This paper proposes a novel approach for scheduling n performance monitoring events onto m hardware per-formance counters, where n> m. Whereas existing scheduling approaches overlook monitored task infor-mation, the proposed algorithm utilizes the monitored task’s behavior and schedules the combination of the most costly events. The proposed algorithm was imple-mented in Linux Perf Event subsystem in kernel space (build 3.11.3), which provides finer granularity and less system perturbation in event monitoring when compared to existing user space approaches. Benchmark exper-iments in PARSEC and SPLASH.2x suites compared the existing round-robin scheme with the proposed rate-of-change approach. Results demonstrate that the rate-of-change a...
Run-time monitoring has been applied in software-intensive systems to detect run-time constraint vio...
International audienceThe aim of this paper is to present a high precision and event-versatile MBPTA...
Identifying design patterns that limit the performance of multi-core algorithms is a challenging tas...
Hardware performance counters are CPU registers that count data loads and stores, cache misses, and ...
The multi-core era has led to a paradigm shift in the interaction between software and hardware. Mul...
International audienceEstimating safe upper bounds on task execution times is required in the design...
The performance monitoring unit (PMU) in multiprocessor system-on-chips (MPSoCs) is at the heart of ...
Abstract—This paper presents an operating system API for monitoring hardware events specifically des...
Hardware performance monitoring counters (PMCs) have proven effective in characterizing application ...
As useful as performance counters are, the meaning of reported aggregate event counts is sometimes q...
infrastructure for performance on multi-core platforms With maturing compiler technologies, compilet...
For industrial systems performance, it is desired to keep the IT infrastructure competitive through ...
Measurement-based timing analysis techniques increasingly rely on the Performance Monitoring Units (...
CPU clock frequency is not likely to be increased significantly in the coming years, and data analys...
This paper aims at designing and implementing a scheduler model for heterogeneous multiprocessor arc...
Run-time monitoring has been applied in software-intensive systems to detect run-time constraint vio...
International audienceThe aim of this paper is to present a high precision and event-versatile MBPTA...
Identifying design patterns that limit the performance of multi-core algorithms is a challenging tas...
Hardware performance counters are CPU registers that count data loads and stores, cache misses, and ...
The multi-core era has led to a paradigm shift in the interaction between software and hardware. Mul...
International audienceEstimating safe upper bounds on task execution times is required in the design...
The performance monitoring unit (PMU) in multiprocessor system-on-chips (MPSoCs) is at the heart of ...
Abstract—This paper presents an operating system API for monitoring hardware events specifically des...
Hardware performance monitoring counters (PMCs) have proven effective in characterizing application ...
As useful as performance counters are, the meaning of reported aggregate event counts is sometimes q...
infrastructure for performance on multi-core platforms With maturing compiler technologies, compilet...
For industrial systems performance, it is desired to keep the IT infrastructure competitive through ...
Measurement-based timing analysis techniques increasingly rely on the Performance Monitoring Units (...
CPU clock frequency is not likely to be increased significantly in the coming years, and data analys...
This paper aims at designing and implementing a scheduler model for heterogeneous multiprocessor arc...
Run-time monitoring has been applied in software-intensive systems to detect run-time constraint vio...
International audienceThe aim of this paper is to present a high precision and event-versatile MBPTA...
Identifying design patterns that limit the performance of multi-core algorithms is a challenging tas...