Area-Efficient Pipelining for FPGA-Targeted High-Level Synthesis

Traditional techniques for pipeline scheduling in high-level synthe-sis for FPGAs assume an additive delay model where each opera-tion incurs a pre-characterized delay. While a good approximation for some operation types, this fails to consider technology mapping, where a group of logic operations can be mapped to a single look-up table (LUT) and together incur one LUT worth of delay. We pro-pose an exact formulation of the throughput-constrained, mapping-aware pipeline scheduling problem for FPGA-targeted high-level synthesis with area minimization being a primary objective. By tak-ing this cross-layered approach, our technique is able to mitigate the pessimism inherent in static delay estimates and reduce the us-age of LUTs and pipeline registers. Experimental results using our method demonstrate improved resource utilization for a number of logic-intensive, real-life benchmarks compared to a state-of-the-art commercial HLS tool for Xilinx FPGAs. 1