On Data Forwarding in Deeply Pipelined Soft Processors

We can design high-frequency soft-processors on FPGAs that exploit deep pipelining of DSP primitives, supported by se-lective data forwarding, to deliver up to 25 % performance improvements across a range of benchmarks. Pipelined, in-order, scalar processors can be small and lightweight but su↵er from a large number of idle cycles due to dependency chains in the instruction sequence. Data forwarding allows us to more deeply pipeline the processor stages while avoid-ing an associated increase in the NOP cycles between depen-dent instructions. Full forwarding can be prohibitively com-plex for a lean soft processor, so we explore two approaches: an external forwarding path around the DSP block execu-tion unit in FPGA logic and using the intrinsic loopback path within the DSP block primitive. We show that in-ternal loopback improves performance by 5 % compared to external forwarding, and up to 25 % over no data forward-ing. The result is a processor that runs at a frequency close to the fabric limit of 500MHz, but without the significant dependency overheads typical of such processors