A C-Based RTL Design Verification Methodology for Complex Microprocessor level

model description I features Polaris macro instruction behavior I register MCV micro-operation I register Cr, As the complexity of high-performance microprocessor in-creases, functional verification becomes more and more dif-ficult and RTL simulation emerges as the bottleneck of the design cycle. In this paper, we suggest C language-based de-sign and verification methodology to enhance the simulation speed instead of the conventional HDL-based methodologies. RTL C model(StreC7) describes the cycle-based behaviors of synchronous circuits and is followed by model refining and optimization using LifeTime Analyzer ( LTA) and Cleanscr. The simulation speed of cycle-based C model makes it pos-sible to test the RTL design with the L‘real-world ” applica-tion programs in the order-of-magnitude faster speed than the commercial event-driven simulators. Using the proposed functional verification methodology, HK486, an intel 80486- compatible microprocessor was successfully designed and verified. internal bus internal bus StreC clock cycle-based RTL register(FF,latch) Phil edge, Phil level Phi2 edge, Phi2 level combinationa