Verification of SoC Design Using Hardware-Software Co-Simulation with High-Level Synthesis

High-level synthesis is a very capable tool that can be used to greatly aid in the development of hardware RTL. It can convert from a C++ specification to SystemVerilog RTL. Using cycle-accurate SystemC to run the RTL, we are able to provide a method to simulate the hardware at the software level using a language that most are familiar with, C++. This allows for increased abilities for verification and testing of the high-level synthesis tool. In addition, it is able to greatly improve our abilities to detect bugs in the original C++ using a hardware-software co-simulation because of the different constraints moving from software to hardware. The framework is fully automated, representing an important step forward toward faster and more effective SoC design verification. Experimental results show that we are able to detect logic bugs from both C/C++ specifications as well as the high-level synthesis engine itself.U of I OnlyUndergraduate senior thesis not recommended for open acces