Data dependences in sequential programs limit paralleliza-tion because extracted threads cannot run independently. Al-though thread-level speculation can avoid the need for precise dependence analysis, communication overheads required to syn-chronize actual dependences counteract the benefits of paral-lelization. To address these challenges, we propose a lightweight architectural enhancement co-designed with a parallelizing com-piler, which together can decouple communication from thread execution. Simulations of these approaches, applied to a pro-cessor with 16 Intel Atom-like cores, show an average of 6.85× performance speedup for six SPEC CINT2000 benchmarks. 1
In recent years, microprocessor manufacturers have shifted their focus from single-core to multi-cor...
With speculative thread-level parallelization, codes that cannot be fully compiler-analyzed are aggr...
Irregular applications have frequent data-dependent memory accesses and control flow. They arise in ...
Data dependences in sequential programs limit parallelization because extracted threads cannot run i...
We describe and evaluate HELIX, a new technique for automatic loop parallelization that assigns succ...
As classic Dennard process scaling fades into the past, power density concerns have driven modern CP...
Improving system performance increasingly depends on exploiting microprocessor parallelism, yet main...
Parallelism has become the primary way to maximize processor performance and power efficiency. But b...
Thesis (Ph. D.)--University of Rochester. Dept. of Computer Science, 2012.Speculative parallelizatio...
As we look to the future, and the prospect of a billion transistors on a chip, it seems inevitable t...
grantor: University of TorontoTo fully exploit the potential of single-chip multiprocessor...
As we look to the future, and the prospect of a bil-lion transistors on a chip, it seems inevitable ...
Graduation date: 2009General purpose computer systems have seen increased performance potential thro...
The basic idea under speculative parallelization (also called thread-level spec-ulation) [2, 6, 7] i...
We present a software approach to design a thread-level data dependence speculation system targeting...
In recent years, microprocessor manufacturers have shifted their focus from single-core to multi-cor...
With speculative thread-level parallelization, codes that cannot be fully compiler-analyzed are aggr...
Irregular applications have frequent data-dependent memory accesses and control flow. They arise in ...
Data dependences in sequential programs limit parallelization because extracted threads cannot run i...
We describe and evaluate HELIX, a new technique for automatic loop parallelization that assigns succ...
As classic Dennard process scaling fades into the past, power density concerns have driven modern CP...
Improving system performance increasingly depends on exploiting microprocessor parallelism, yet main...
Parallelism has become the primary way to maximize processor performance and power efficiency. But b...
Thesis (Ph. D.)--University of Rochester. Dept. of Computer Science, 2012.Speculative parallelizatio...
As we look to the future, and the prospect of a billion transistors on a chip, it seems inevitable t...
grantor: University of TorontoTo fully exploit the potential of single-chip multiprocessor...
As we look to the future, and the prospect of a bil-lion transistors on a chip, it seems inevitable ...
Graduation date: 2009General purpose computer systems have seen increased performance potential thro...
The basic idea under speculative parallelization (also called thread-level spec-ulation) [2, 6, 7] i...
We present a software approach to design a thread-level data dependence speculation system targeting...
In recent years, microprocessor manufacturers have shifted their focus from single-core to multi-cor...
With speculative thread-level parallelization, codes that cannot be fully compiler-analyzed are aggr...
Irregular applications have frequent data-dependent memory accesses and control flow. They arise in ...