Abstract—This paper proposes Carousel, a mechanism to manage local memory space, i.e. cache or scratchpad memory (SPM), such that inter-task interference is completely eliminated. The cost of saving and restoring the local memory state across context switches is explicitly handled by the preempting task, rather than being imposed implicitly on preempted tasks. Unlike earlier attempts to eliminate inter-task interference, Carousel allows each task to use as much local memory space as it requires, permitting the approach to scale to large numbers of tasks. Carousel is experimentally evaluated using a simulator. We demonstrate that preemption has no effect on task execution times, and that the Carousel technique compares well to the convention...
Predictability is one of the key properties of hard real-time systems. A system is predictable when ...
The large latency of memory accesses in modern computers is a key obstacle in achieving high process...
We introduce Selfish-LRU, a variant of the LRU (least recently used) cache replacement policy that i...
Caches help reduce the average execution time of tasks due to their fast operational speeds. However...
We describe and evaluate explicit reservation of cache memory to reduce the cache-related preemption...
Over the last 20 years, the performance gap between CPU and memory has been steadily increasing. As ...
International audienceThe design of tailored hardware has proven a successful strategy to reduce the...
Row buffer locality is a consequence of programs' inherent spatial locality that the memory system c...
Caches have become invaluable for higher-end architectures to hide, in part, the increasing gap betw...
Cache memories have been historically avoided in real-time systems because of their unpredictable be...
Given the emerging dominance of chip-multiprocessor (CMP) systems, an important research problem con...
Abstract—A central issue for verifying the schedulability of hard real-time systems is the correct e...
Hardware trends have produced an increasing disparity between processor speeds and memory access tim...
A central issue for verifying the schedulability of hard real-time systems is the correct evaluation...
While many parallel applications exhibit good spatial locality, other important codes in areas like ...
Predictability is one of the key properties of hard real-time systems. A system is predictable when ...
The large latency of memory accesses in modern computers is a key obstacle in achieving high process...
We introduce Selfish-LRU, a variant of the LRU (least recently used) cache replacement policy that i...
Caches help reduce the average execution time of tasks due to their fast operational speeds. However...
We describe and evaluate explicit reservation of cache memory to reduce the cache-related preemption...
Over the last 20 years, the performance gap between CPU and memory has been steadily increasing. As ...
International audienceThe design of tailored hardware has proven a successful strategy to reduce the...
Row buffer locality is a consequence of programs' inherent spatial locality that the memory system c...
Caches have become invaluable for higher-end architectures to hide, in part, the increasing gap betw...
Cache memories have been historically avoided in real-time systems because of their unpredictable be...
Given the emerging dominance of chip-multiprocessor (CMP) systems, an important research problem con...
Abstract—A central issue for verifying the schedulability of hard real-time systems is the correct e...
Hardware trends have produced an increasing disparity between processor speeds and memory access tim...
A central issue for verifying the schedulability of hard real-time systems is the correct evaluation...
While many parallel applications exhibit good spatial locality, other important codes in areas like ...
Predictability is one of the key properties of hard real-time systems. A system is predictable when ...
The large latency of memory accesses in modern computers is a key obstacle in achieving high process...
We introduce Selfish-LRU, a variant of the LRU (least recently used) cache replacement policy that i...