International audienceThe design of tailored hardware has proven a successful strategy to reduce the timing analysis overhead for (hard) real-time systems. The stack cache is an example of such a design that was shown to provide good average-case performance, while remaining easy to analyze. So far, however, the analysis of the stack cache was limited to individual tasks, ignoring aspects related to multitasking. A major drawback of the original stack cache design is that, due to its simplicity, it cannot hold the data of multiple tasks at the same time. Consequently, the entire cache content needs to be saved and restored when a task is preempted. We propose (a) an analysis exploiting the simplicity of the stack cache to bound the overhead...
International audience<p>The growing complexity of modern computer architectures increasingly compli...
With the rapid growth of complex hardware features, timing analysis has become an increasingly diffi...
A common mechanism to perform hardware-based prefetching for regular accesses to arrays and chained...
International audienceThe design of tailored hardware has proven a successful strategy to reduce the...
Caches have become invaluable for higher-end architectures to hide, in part, the increasing gap betw...
Abstract. In this paper, we propose a timing analysis approach for preemptive multi-tasking real-tim...
Cache locking improves timing predictability at the cost of performance. We explore a novel approach...
International audienceThe design of tailored hardware has proven a successful strategy to reduce the...
Caches have become invaluable for higher-end architectures to hide, in part, the increasing gap betw...
23rd IEEE Real-Time and Embedded Technology and Applications Symposium, RTAS 2017, Pittsburg, PA, US...
The gap between processor and memory speed appears as a serious bottleneck in improving the performa...
Cache memory is used in almost all computer systems today to bridge the ever increasing speed gap be...
International audienceUtilizing a stack cache in a real-time system can aid predictability by avoidi...
Dependable real-time systems are essential to time-critical applications. The systems that run these...
Caches have become invaluable for higher-end architectures to hide, in part, the increasing gap betw...
International audience<p>The growing complexity of modern computer architectures increasingly compli...
With the rapid growth of complex hardware features, timing analysis has become an increasingly diffi...
A common mechanism to perform hardware-based prefetching for regular accesses to arrays and chained...
International audienceThe design of tailored hardware has proven a successful strategy to reduce the...
Caches have become invaluable for higher-end architectures to hide, in part, the increasing gap betw...
Abstract. In this paper, we propose a timing analysis approach for preemptive multi-tasking real-tim...
Cache locking improves timing predictability at the cost of performance. We explore a novel approach...
International audienceThe design of tailored hardware has proven a successful strategy to reduce the...
Caches have become invaluable for higher-end architectures to hide, in part, the increasing gap betw...
23rd IEEE Real-Time and Embedded Technology and Applications Symposium, RTAS 2017, Pittsburg, PA, US...
The gap between processor and memory speed appears as a serious bottleneck in improving the performa...
Cache memory is used in almost all computer systems today to bridge the ever increasing speed gap be...
International audienceUtilizing a stack cache in a real-time system can aid predictability by avoidi...
Dependable real-time systems are essential to time-critical applications. The systems that run these...
Caches have become invaluable for higher-end architectures to hide, in part, the increasing gap betw...
International audience<p>The growing complexity of modern computer architectures increasingly compli...
With the rapid growth of complex hardware features, timing analysis has become an increasingly diffi...
A common mechanism to perform hardware-based prefetching for regular accesses to arrays and chained...