Timing Anomalies Reloaded

Computing tight WCET bounds in the presence of timing anomalies – found in almost any modern hard-ware architecture – is a major challenge of timing analysis. In this paper, we renew the discussion about timing anomalies, demonstrating that even simple hard-ware architectures are prone to timing anomalies. We furthermore complete the list of timing-anomalous cache replacement policies, proving that the most-recently-used replacement policy (MRU) also exhibits a domino effect