The TDCPix is a hybrid pixel detector readout ASIC designed for the NA62 GigaTracker detec-tor. The asynchronously operating pixel array consists of 1800 pixels, each 300x300 µm2. The requirements are a single-hit timing resolution better than 200 ps RMS and a read-out efficiency of 99 % or better in the presence of a beam rate between 800MHz and 1GHz. The discrimina-tor time walk effect is compensated by time-over-threshold discriminators connected to an array of 360 dual TDC channels. The TDCpix processes up to 210Mhits/s and provides the hit data without the need of a trigger in a continuous data stream via four 3.2Gb/s serialisers. Under test since January 2014, the TDCPix chip is fully functional and shows excellent performance
The Gigatracker is a hybrid silicon pixel detector developed to track the highly intense NA62 hadron...
The Gigatracker is a hybrid silicon pixel detector developed to track the highly intense NA62 hadron...
The paper describes the design of a front-end chip for hybrid pixel detectors optimized for good tim...
The TDCPix is a hybrid pixel detector readout ASIC designed for the NA62 GigaTracker detec- tor. The...
The TDCpix is a novel pixel readout ASIC for the NA62 Gigatracker detector. NA62 is a new experiment...
NA62 is an experiment under development at the CERN Super Proton Synchrotron, aiming at measuring ul...
The TDCpix ASIC is the readout chip for the Gigatracker station of the NA62 experiment. Each station...
One of the most challenging detectors of the NA62 experiment is the silicon tracker, called Gigatrac...
NA62 is an experiment under development at the CERN Super Proton Synchrotron, aiming at measuring ul...
The architecture and characterisation of the End Of Column demonstrator readout ASIC for the NA62 Gi...
The TDCpix ASIC is the readout chip for the Gigatracker station of the NA62 experiment. Each station...
AbstractNA62 is an experiment under development at the CERN Super Proton Synchrotron, aiming at meas...
The architecture and characterisation of the NA62 GigaTracker End of Column Demonstrator Hybrid Pixe...
We present the ASIC development for the readout electronics of the Gigatracker pixel detector of NA6...
The beam spectrometer of the NA62 experiment, named Gigatracker, has to perform single track reconst...
The Gigatracker is a hybrid silicon pixel detector developed to track the highly intense NA62 hadron...
The Gigatracker is a hybrid silicon pixel detector developed to track the highly intense NA62 hadron...
The paper describes the design of a front-end chip for hybrid pixel detectors optimized for good tim...
The TDCPix is a hybrid pixel detector readout ASIC designed for the NA62 GigaTracker detec- tor. The...
The TDCpix is a novel pixel readout ASIC for the NA62 Gigatracker detector. NA62 is a new experiment...
NA62 is an experiment under development at the CERN Super Proton Synchrotron, aiming at measuring ul...
The TDCpix ASIC is the readout chip for the Gigatracker station of the NA62 experiment. Each station...
One of the most challenging detectors of the NA62 experiment is the silicon tracker, called Gigatrac...
NA62 is an experiment under development at the CERN Super Proton Synchrotron, aiming at measuring ul...
The architecture and characterisation of the End Of Column demonstrator readout ASIC for the NA62 Gi...
The TDCpix ASIC is the readout chip for the Gigatracker station of the NA62 experiment. Each station...
AbstractNA62 is an experiment under development at the CERN Super Proton Synchrotron, aiming at meas...
The architecture and characterisation of the NA62 GigaTracker End of Column Demonstrator Hybrid Pixe...
We present the ASIC development for the readout electronics of the Gigatracker pixel detector of NA6...
The beam spectrometer of the NA62 experiment, named Gigatracker, has to perform single track reconst...
The Gigatracker is a hybrid silicon pixel detector developed to track the highly intense NA62 hadron...
The Gigatracker is a hybrid silicon pixel detector developed to track the highly intense NA62 hadron...
The paper describes the design of a front-end chip for hybrid pixel detectors optimized for good tim...