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Original Aims of the Project The implementation of a processor on an FPGA using combinators as the instruction set, and a compiler to convert a subset of ML to the target instruction set. The project set out to build an architecture which would utilize both the on-chip and off-chip memory in a scalable way. The resulting system would be evaluated by running a series of programs written in the ML subset language and contrasting it to a comparable implementation. Work Completed All aims set out in the original proposal have been fulfilled. A combinator processor has been built on an Altera DE2 board and can scale to perform large computations. The compiler supports a powerful subset of ML and a type system has been built for the language. In addition to the original aims set out in the proposal, basic imperative features are supported. These have been used to build more powerful applications which test the scalability of the processor. Finally, the system has been compared to an existing research implementation and was found to perform favourably