Power efficient branch prediction through early identification of branch addresses

Ever increasing performance requirements have elevated deeply pipelined architectures to a standard even in the em-bedded processor domain, requiring the incorporation of dy-namic branch prediction subsystems to hide the execution latency of control-altering instructions. In this paper a low power early branch identification technique which enables the design of extremely power-efficient branch predictors and BTBs is proposed. Through static extraction of program in-formation regarding the distance to subsequent branches, this technique enables the calculation of the next branch address as soon as the direction of the current branch has been pre-dicted. Early identification of branch addresses enables a complete elimination of the power hungry BTB lookups nor-mally occurring at every execution cycle, as well as a just-in-time wake-up mechanism when accessing “hibernating ” en-tries in complex predictors, switched to power-saving mode to reduce leakage power dissipation. A cost-efficient Branch Identification Unit (BIU) to calculate branch addresses is presented and analyzed in terms of power and timing char-acteristics. The effectiveness of the proposed BTB access policy and predictor wake-up mechanism is also confirmed by the simulation results of the SPECint 2000 and Media-bench benchmarks