Branch prediction techniques for low-power VLIW processors

Main goal of the paper is to introduce a branch prediction scheme suitable for energy-efficient VLIW (Very Long In-struction Word) processors aiming at reducing the energy associated with the prediction phase by filtering the accesses to the branch predictor block. To analyze the effectiveness of the proposed low-power branch prediction scheme, we combined it to some well-known dynamic branch prediction techniques suitable for VLIW processors. Experimental re-sults have been carried out on Lx, a 4-issue VLIW architec-ture with 6-stage pipeline. The proposed solution implies a performance improvement of 7 % on average and an average energy reduction of 15%