This paper describes an experiment in which parallel routing is performed on a medium grained hypercube parallel proces-sor having 64 processing elements. Each node is a complete 32-bit computer with 128 K-bytes of memory and is con-nected to the other nodes via a direct hypercube interconnec-tion network. A new parallel routing algorithm was devel-oped to exploit this parallel structure. It is a three step algo-rithm consisting of a global routing step, a boundary crossing placement step, and a detailed routing step. All steps can be performed in parallel. When applied to a standard benchmark it was able to route 95 % of the wires. The algorithm was also executed on a large mainframe computer using the same benchmark. The execution time wa...
Many parallel algorithms exhibit a hypercube communication topology. Such algorithms can easily be e...
With the increasing density of components on Printed Circuit Boards (PCBs) and the advancement of fa...
We have implemented an FPGA routing algorithm on a shared memory multi-processor using the Galois AP...
The routing problem of VLSI layout design is computationally very expensive because of the inherent ...
Gate-arrays are the most common design style for semicus-tom VLSI integrated circuits. An important ...
Many times, routing of signal nets in the layout design of VLSI circuits turns out to be a bottlenec...
Data parallel programming provides a simple and powerful framework for designing parallel algorithms...
Gate-arrays are the most common design style for semicustom VLSI integrated circuits. An important p...
The computational requirements for high quality synthesis, analysis, and verification of VLSI design...
In this paper, we propose three different parallel algorithms based on a state-of-the-art global rou...
We consider several basic problems in VLSI routing such as river routing between rectangles, routing...
We propose a parallel global routing algorithm that con-currently processes routing subproblems corr...
Multicomputer Routing Techniques by Melanie L. Fulgham Chairperson of Supervisory Committee Professo...
In this thesis, we explore various parallel processing methods for concurrent multi-layer VLSI routi...
A parallel sorting algorithm for sorting n elements evenly distributed over 2d =p nodes of a d-dimen...
Many parallel algorithms exhibit a hypercube communication topology. Such algorithms can easily be e...
With the increasing density of components on Printed Circuit Boards (PCBs) and the advancement of fa...
We have implemented an FPGA routing algorithm on a shared memory multi-processor using the Galois AP...
The routing problem of VLSI layout design is computationally very expensive because of the inherent ...
Gate-arrays are the most common design style for semicus-tom VLSI integrated circuits. An important ...
Many times, routing of signal nets in the layout design of VLSI circuits turns out to be a bottlenec...
Data parallel programming provides a simple and powerful framework for designing parallel algorithms...
Gate-arrays are the most common design style for semicustom VLSI integrated circuits. An important p...
The computational requirements for high quality synthesis, analysis, and verification of VLSI design...
In this paper, we propose three different parallel algorithms based on a state-of-the-art global rou...
We consider several basic problems in VLSI routing such as river routing between rectangles, routing...
We propose a parallel global routing algorithm that con-currently processes routing subproblems corr...
Multicomputer Routing Techniques by Melanie L. Fulgham Chairperson of Supervisory Committee Professo...
In this thesis, we explore various parallel processing methods for concurrent multi-layer VLSI routi...
A parallel sorting algorithm for sorting n elements evenly distributed over 2d =p nodes of a d-dimen...
Many parallel algorithms exhibit a hypercube communication topology. Such algorithms can easily be e...
With the increasing density of components on Printed Circuit Boards (PCBs) and the advancement of fa...
We have implemented an FPGA routing algorithm on a shared memory multi-processor using the Galois AP...