A Microserver View on HTMT: New Benchmarks and Applications

Abstract. HTMT is an ambitious new architecture combining cutting edge technologies to reach peta op performance sooner than current technology trends allow. It is a massively parallel architec-ture with multi-threaded hardware and a multi-level memory hierarchy. Microservers provide a new perspective for viewing this memory hierarchy whereby memory is actively involved in process execu-tion. This work discusses the microserver memory semantics and initial HTMT execution models to analyze applications at each level of the system hierarchy and to develop user-level functions for ex-pressing this inherent concurrency and parallelism. In order to do this we studied several applications to model the control and data ow within the HTMT hierarchy and developed pseudo-code representing the user-level functions necessary to express application concurrency and parallelism.