The traditional algorithm of Stockmeyer for area minimization of slicing oorplans has time (and space) complexity O(n 2) in the worst case, or O(n logn) for balanced slicing. For more than a decade, it is consid-ered the best possible. In this paper, we present a new algorithm of worst-case time (and space) complexity O(n logn), where n is the total number of realizations for the basic blocks, regardless whether the slicing is balanced or not. We also prove (n logn) is the lower bound on the time complexity of any area minimization algo-rithm. Therefore, the new algorithm not only nds the optimal realization, but also has an optimal run-ning time
ABSTRACT modules can be handled in constraint graphs efficiently. This Floorplan area minimization i...
[[abstract]]We consider in this paper the problem of slicing floorplan design with boundary-constrai...
Slicing tree has been an effective tool for VLSI floorplan de-sign. Floorplanners using slicing tree...
[[abstract]]Stockmeyer in Ref. 1 presented an optimal algorithm to solve the floorplan area optimiza...
[[abstract]]A well known approach for the floorplan area optimization problem is to first determine ...
[[abstract]]A well known approach for the floorplan are optimization problem is to first determine a...
[[abstract]]An optimal algorithm for the floorplan area optimization problem is presented. The algor...
The first stage in hierarchical approaches to floorplan design determines certain topological relati...
The building blocks in a given floor-plan may have several possible physical implementations yie1din...
[[abstract]]Studies the time complexity of L. Stockmeyer's technique (1993) to solve the floorplan a...
The first stage in hierarchical approaches to floorplan design determines certain topological relati...
The first stage in hierarchical approaches to floorplan design determines certain topological relati...
The first stage in hierarchical approaches to floorplan design determines certain topological relati...
The first stage in hierarchical approaches to floorplan design determines certain topological relati...
[[abstract]]An optimal algorithm for the VLSI floorplan area optimization problem is presented. The ...
ABSTRACT modules can be handled in constraint graphs efficiently. This Floorplan area minimization i...
[[abstract]]We consider in this paper the problem of slicing floorplan design with boundary-constrai...
Slicing tree has been an effective tool for VLSI floorplan de-sign. Floorplanners using slicing tree...
[[abstract]]Stockmeyer in Ref. 1 presented an optimal algorithm to solve the floorplan area optimiza...
[[abstract]]A well known approach for the floorplan area optimization problem is to first determine ...
[[abstract]]A well known approach for the floorplan are optimization problem is to first determine a...
[[abstract]]An optimal algorithm for the floorplan area optimization problem is presented. The algor...
The first stage in hierarchical approaches to floorplan design determines certain topological relati...
The building blocks in a given floor-plan may have several possible physical implementations yie1din...
[[abstract]]Studies the time complexity of L. Stockmeyer's technique (1993) to solve the floorplan a...
The first stage in hierarchical approaches to floorplan design determines certain topological relati...
The first stage in hierarchical approaches to floorplan design determines certain topological relati...
The first stage in hierarchical approaches to floorplan design determines certain topological relati...
The first stage in hierarchical approaches to floorplan design determines certain topological relati...
[[abstract]]An optimal algorithm for the VLSI floorplan area optimization problem is presented. The ...
ABSTRACT modules can be handled in constraint graphs efficiently. This Floorplan area minimization i...
[[abstract]]We consider in this paper the problem of slicing floorplan design with boundary-constrai...
Slicing tree has been an effective tool for VLSI floorplan de-sign. Floorplanners using slicing tree...