VSSAD/Alpha Development Group

Hardly predictable data addresses in man), irregular applica-tions have rendered prefetching ineffective. In many cases, the only accurate way to predict these addresses is to directly execute the code that generates them. As multithreaded architectures be-come increasingly popular, one attractive approach is to use idle threads on these machines to perform pre-execution--essentially combined act of speculative address generation and prefetching--to accelerate the main thread. In this paper, we propose such a pre-execution technique for simultaneous multithreading (SMT) processors. By using software to control pre-execution, we are able to handle some of the most important access patterns that are ~'pically difficult to prefetch. Compared with existing work on pre-execution, our technique is significantly simpler to implement (e.g., no integration of pre-execution results, no need of shorten-ing programs for pre-execution, and no need of special hardware to copy register values upon thread spawns). Consequentl3; only minimal extensions to SMT machines are required to support our technique. Despite its simplicit),, our technique offers an average speedup of 24 % in a set of irregular applications, which is a 19% speedup over state-of-the-art software-controlled prefetching. 1