Future execution: A hardware prefetching technique for chip multiprocessors

This paper proposes a new hardware technique for us-ing one core of a CMP to prefetch data for a thread run-ning on another core. Our approach simply executes a copy of all non-control instructions in the prefetching core af-ter they have executed in the primary core. On the way to the second core, each instruction’s output is replaced by a prediction of the likely output that the nth future instance of this instruction will produce. Speculatively executing the resulting instruction stream on the second core issues load requests that the main program will probably refer-ence in the future. Unlike previously proposed thread-based prefetching approaches, our technique does not need any thread spawning points, features an adjustable lookahead distance, does not require complicated analyzers to extract prefetching threads, is recovery-free, and necessitates no storage for the prefetching threads. We demonstrate that for the SPECcpu2000 benchmark suite, our mechanism sig-nificantly increases the prefetching coverage and improves the primary core’s performance by 10 % on average over a baseline that already includes an aggressive hardware stream prefetcher. We further show that our approach works well in combination with runahead execution.