A Flexible Platform Framework for Rapid Transactional Memory Systems Prototyping and Evaluation

Transactional memory (TM) is an emerging synchro-nization mechanism that aims to solve most of the difficul-ties inherent in lock-based approaches. TM implementa-tions may either rely on special hardware (HTM) or em-ploy a software-only (STM) technique. While STM can be implemented and evaluated in current machines, HTM re-quires hardware modification and a prototyping infrastruc-ture. We present in this paper a flexible platform frame-work for rapid prototyping and evaluation of HTM sys-tems. Platform components such as cache, memory and interconnection medium are implemented using SystemC and Transaction-Level Modeling (TLM). Processors are de-scribed in an Architecture Description Language (ADL) which makes it practical to change the Instruction Set Ar-chitecture (ISA), since simulators and binary utilities are automatically generated by the ADL toolset. The resulting flexibility allows designers to explore the design space in a simple and uniform manner. We illustrate the platform through a case study based on the original HTM proposed by Herlihy and Moss. Simulation results are shown for mi-crobenchmarks supporting up to 256 processors. 1