Parallelization Strategies for Network Interface Firmware

Typical data-intensive embedded applications have large amounts of instruction-level parallelism that is often ex-ploited with wide-issue VLIW processors. In contrast, event-driven embedded applications are believed to have very little instruction-level parallelism, so these applica-tions often utilize much simpler processor cores. Pro-grammable network interface cards, for example, utilize thread-level parallelism across multiple processor cores to handle multiple events concurrently. However, the syn-chronization required to access a device’s shared external I/O interfaces lead to scalability limitations and diminish-ing returns. This paper compares the instruction-level parallelism versus thread-level parallelism in control-dominated net-work interface firmware and finds that though thread-level parallelism scales to higher levels of performance, there exists a significant amount of instruction-level parallelism that can be exploited by traditional wide-issue VLIW pro-cessors. For example, a seven-wide VLIW-based net-work interface architecture achieves approximately the same frame throughput as a two-way single-issue mul-tiprocessor implementation. This motivates the use of wide-issue VLIW architectures typically used for media and signal processing workloads to extract parallelism left previously unutilized by existing thread-level approaches. This paper advocates that a combination of these two ap-proaches should lead to even higher levels of performance than today’s control-oriented embedded systems architec-tures.