This paper presents a new approach to retarget existing software at the assembly level from one instruction set to another instruction set. The approach is based on abstracting the instruction set as the symbolic transitions of the machine states, especially focuses on translating Intel x86 instruction set into another efficient RISC-based core instruction set. The retargeting process is modeled as a planning process that finds a plan which brings the processor from the same initial states to the same final states as the original software. The assembly-to-assembly retargeting capability helps renovating the existing software investment and shortening the period of time-to-market when upgrading to processor with newer instruction sets. 1
International audienceEfficient architecture exploration and design of application specific instruct...
The core tool in Application-Specific Instruction Set Processor (ASIP) design toolsets is a retarget...
embedded systems. Retargetable code generation is a co-designing method to map a high-level software...
This paper presents a new approach to retarget existing software at the assembly level from one inst...
RISC instruction set, x86 instruction set This paper presents an interesting approach to retargeting...
The goal of this work is to detect and transform instruction idioms used in modern compilers. These ...
Machine code disassembling is a process of transforming binary machine code into assembly code. The ...
International audienceEmbedded core processors are becoming a vital part of today's system-on-a-chi...
Instruction-set architecture (ISA) simulators are an integral part of today's processor and software...
The AVIV retargetable code generator produces optimized machine code for target processors with diff...
This work aims to reduce the power consumed in the instruction memory of instruction set processors ...
Abstract—Machine-code decompilation is a reverse-engineering discipline focused on reverse compilati...
UnrestrictedThe design of hardware and software for embedded systems is well understood. But the co...
This abstract presents a design aid called ReCode, and describes its use in the analysis of existing...
Abstract—This paper presents the design alternatives for reconfigurable instruction set processors (...
International audienceEfficient architecture exploration and design of application specific instruct...
The core tool in Application-Specific Instruction Set Processor (ASIP) design toolsets is a retarget...
embedded systems. Retargetable code generation is a co-designing method to map a high-level software...
This paper presents a new approach to retarget existing software at the assembly level from one inst...
RISC instruction set, x86 instruction set This paper presents an interesting approach to retargeting...
The goal of this work is to detect and transform instruction idioms used in modern compilers. These ...
Machine code disassembling is a process of transforming binary machine code into assembly code. The ...
International audienceEmbedded core processors are becoming a vital part of today's system-on-a-chi...
Instruction-set architecture (ISA) simulators are an integral part of today's processor and software...
The AVIV retargetable code generator produces optimized machine code for target processors with diff...
This work aims to reduce the power consumed in the instruction memory of instruction set processors ...
Abstract—Machine-code decompilation is a reverse-engineering discipline focused on reverse compilati...
UnrestrictedThe design of hardware and software for embedded systems is well understood. But the co...
This abstract presents a design aid called ReCode, and describes its use in the analysis of existing...
Abstract—This paper presents the design alternatives for reconfigurable instruction set processors (...
International audienceEfficient architecture exploration and design of application specific instruct...
The core tool in Application-Specific Instruction Set Processor (ASIP) design toolsets is a retarget...
embedded systems. Retargetable code generation is a co-designing method to map a high-level software...