Hardware Implementation of Communication Protocols modeled by Concurrent EFSMs with Multi-way Synchronization

In this paper, we propose a technique to implement communication protocols as hardware circuits using a model of concurrent EFSMs with multi-way synchronization. Since use of multi-way synchro-nization enables simple and comprehensible specifications of re-cent communication protocols which frequently use complicated mechanisms such as mutual exclusion and dynamic job assign-ment, the proposed model is expected to reduce development cost in designing/developing such protocols. We implement specifica-tions described in the model so that EFSMs work synchronously with the same clock, and that the synchronization mechanism for checking executability of each tuple of synchronizing transitions is implemented as a combinational logic circuit. Through some experiments, we have confirmed that the proposed technique can synthesize hardware circuits with relatively good performances for practical use. General Terms high-level synthesis, concurrent EFSMs, multi-way synchroniza-tion, LOTOS, communication protocols 1