Multi-domain Communication Scheduling For FPGA-based Logic Emulation

Communication scheduling is a technique used by many parallel verification systems to pipeline data signals across shared physical wires. This scheduling approach makes it possible to multiplex processing component pins across numerous logical signals, effectively overcoming pin limitations. While it is generally straightforward to derive a fixed relationship between the verification system clock which controls communication and the numerous phase-related clocks of a design under test, mapping complications arise if a user design contains multiple clocks that operate asynchronously to each other. Specifically, multi-clock domain behavior makes it difficult to ensure that reconvergent multi-FPGA paths that are sourced and sampled by multiple asynchronous design clocks can be evaluated accurately. In this paper, we describe scheduling and synthesis techniques that address the reconvergent fanout proble