High-Bandwidth Address Translation for Multiple-Issue

In an effort to push the envelope of system performance, mi-croprocessor designs are continually exploiting higher levels of instruction-level parallelism, resulting in increasing bandwidth de-mands on the address translation mechanism. Most current micro-processor designs meet this demand with a multi-ported TLB. While this design provides an excellent hit rate at each port, its access la-tency and area grow very quickly as the number of ports is increased. As bandwidth demands continue to increase, multi-ported designs will soon impact memory access latency. We present four high-bandwidth address translation mechanisms with latency and area characteristics that scale better than a multi-ported TLB design. We extend traditional high-bandwidth memory design techniques to address translation, developing interleaved and multi-level TLB designs. In addition, we introduce two new designs crafted specifically for high-bandwidth address translation. Piggy-back ports are introduced as a technique to exploit spatial locality in simultaneous translation requests, allowing accesses to the same vir-tual memory page to combine their requests at the TLB access port. Pretranslation is introduced as a technique for attaching translations to base register values, making it possible to reuse a single transla-tion many times. We perform extensive simulation-based studies to evaluate our designs. We vary key system parameters, such as processor model, page size, and number of architected registers, to see what effects these changes have on the relative merits of each approach. A num-ber of designs show particular promise. Multi-level TLBs with as few as eight entries in the upper-level TLB nearly achieve the per-formance of a TLB with unlimited bandwidth. Piggyback ports combined with a lesser-ported TLB structure, e.g., an interleaved or multi-ported TLB, also perform well. Pretranslation over a single-ported TLB performs almost as well as a same-sized multi-level TLB with the added benefit of decreased access latency for physi-cally indexed caches.