Performance evaluation of TLB consistency solutions in large-scale shared-memory multiprocessors with consistent caches

Three methods to maintain translation lookaside buffer (TLB) consistency in highly-parallel, shared-memory multiprocessors (HPSMMs) without consistent caches, Read-locked TLBs, Validation, and Memory-based TLBs, were suggested by Teller. The state-of-the-art of microprocessors and shared-memory multiprocessors has changed significantly since the time when these solutions were first introduced, thus, they may not be suitable for state-of-the-art, cache-consistent HPSMMs. Accordingly, we examine these solutions and modify them as is necessary to implement them in cache-consistent HPSMMs. In addition, we study the performance of two solutions, revised-Validation and Memory-based TLBs, in today\u27s cache-consistent HPSMMs via an augmented version of the execution-driven simulator, Rice Simulator for ILP Multiprocessors (RSIM+), which models wormhole-routed networks interconnecting N processors and N memory modules and is capable of simulating a range of multiprocessor architectures. The simulations are driven by Stanford ParalleL Applications for SHared memory (SPLASH-2) application programs (FFT, LU, RADIX, and WATER). For the systems and workloads studied, the results of the simulations show that Memory-based TLBs outperforms revised-Validation as the TLB size or the number of paging arenas increases