Interface design and system impact analysis of a message-handling processor for fine-grain multithreading

Graduation date: 1995There appears to be a broad agreement that high-performance computers of the future will be\ud Massively Parallel Architectures (MPAs), where all processors are interconnected by a high-speed\ud network. One of the major problems with MPAs is the latency observed for remote operations. One\ud technique to hide this latency is multithreading. In multithreading, whenever an instruction accesses a\ud remote location, the processor switches to the next available thread waiting for execution. There have\ud been a number of architectures proposed to implement multithreading. One such architecture is the\ud Threaded Abstract Machine (TAM). It supports fine-grain multithreading by an appropriate compilation\ud strategy rather that through elaborate hardware. Experiments on TAM have already shown that fine-grain\ud multithreading on conventional architectures can achieve reasonable performance.\ud However, a significant deficiency of the conventional design in the context of fine-grain program\ud execution is that the message handling is viewed as an appendix rather than as an integral, essential part\ud of the architecture. Considering that message handling in TAM can constitute as much as one fifth to one\ud half of total instructions executed, special effort must be given to support it in the underlying hardware.\ud This thesis presents the design modifications required to efficiently support message handling for\ud fine-grain parallelism on stock processors. The idea of having a separate processor is proposed and\ud extended to reduce the overhead due to messages. A detailed hardware is designed to establish the\ud interface between the conventional processor and the message-handling processor. At the same time, the\ud necessary cycle cost required to guarantee atomicity between the two processors is minimized. However,\ud the hardware modifications are kept to a minimum so as not to disturb the original functionality of a\ud conventional RISC processor. Finally, the effectiveness of the proposed architecture is analyzed in terms\ud of its impact on the system. The distribution of the workload between both processors is estimated to\ud indicate the potential speed-up that can be achieved with a separate processor to handle messages