Memory Consistency and Event Ordering in Scalable Shared-Memory Multiproc, essors

Scalable shared-memory multiprocessors distribute mem-ory among the processors and use scalable interconnec-tion networks to provide high bandwidth and low latency communication. In addition, memory accesses are cached, buffered, and pipelined to bridge the gap between the slow shared memory and the fast processors. Unless care-fully controlled, such architectural optimizations can cause memory accesses to be executed in an order different from what the programmer expects. The set of allowable mem-ory access orderings forms the memory consistency model or event ordering model for an architecture. This paper introduces a new model of memory con-sistency, called release consistency, that allows for more buffering and pipelining than previously proposed models. A framework for classifying shared accesses and reasoning about event ordering is developed. The release consistency model is shown to be equivalent to the sequential consis-tency model for parallel programs with sufficient synchro-nization. Possible performance gains from the less strict constraints of the release consistency model are explored. Finally, practical implementation issues are discussed, con-centrating on issues relevant to scalable architectures.