Bitwise and Dictionary Modeling for Code Compression on Transport Triggered Architectures

Program code size has become a critical design constraint of embedded systems. Code compression is one of the approaches to reduce the program code size; it results in smaller memories and reduced cost of the chip. In this paper, bitwise and dictionary modeling schemes for code compression are evaluated on transport triggered architec-ture processors, designed for four applications taken from different application domains. Results of the bitwise mod-eling scheme are promising, whereas the dictionary mod-eling scheme needs further improvements to be profitable. KEY WORDS transport triggered architecture, customizable processor ar-chitecture, digital signal processing, program compression, bitwise modeling, dictionary modeling