Data memory minimisation for synchronous data flow graphs emulated on dsp-fpga targets

The paper presents an algorithm to determine the close-to-smallest possible data buffer sizes for arbitrary synchronous data flow (SDF) applications, such that we can guarantee the exis-tence of a deadlock free schedule. The presented algorithm fits in the design flow of GRAPE, an environment for the emulation and implementation of digital signal processing (DSP) systems on arbitrary target architectures, consisting of programmable DSP processors and FPGAs. Reducing the size of data buffers is of high importance when the application will be mapped on Field Programmable Gate Arrays (FPGA), since register resources are rather scarce. 1. Introduction an